Use
Makes names defined in a library or package directly visible within another
region of VHDL code. Typically written either at the top of an entity, giving
access to common definitions from a package, or at the top of a configuration,
giving access to the entities and architectures from a library.
Syntax
use SelectedName, ... ;
SelectedName = {typically one of}
LibraryName.PackageName.ItemName
LibraryName.PackageName.all
LibraryName.ItemName
LibraryName.all
Where
See Declaration, (VHDL) File, Configuration
Rules
If two uses attempt to make the same name visible from different places, then
neither is visible. Similarly, a name made visible by a use will be hidden by a
local definition of the same name.
Things to remember
use Lib.Pack.TypeName; does not make enumeration literals, operators or
implicit declarations visible!
Tips
If two uses cancel each other out, the hidden item can be referenced using its
selected name (e.g. Lib.Pack.Item).
Example
use IEEE.Std_logic_1164.all; -- The contents of the package
use WORK.Arith_Ops; -- The package name only
use CMOS_TECH.all; -- All the entities in the library
See Also
Library, (VHDL) File, Package, Name
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